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SM5847af nippon precision circuits? nippon precision circuits inc. high-?elity digital audio, multi-function digital filter overview the SM5847af is a 4/8-times oversampling (inter- polation), 2-channel, linear-phase fir, multi-func- tion digital ?ter for digital audio reproduction equipment. it features independent left and right- channel digital deemphasis ?ters and soft muting function. the input/output interface supports input data in 16/18/20/24-bit words, and output data in 18/20/22/24-bit words in either 4-times or 8-times oversampling selectable output mode. the internal system clock operates at either 192fs or 256fs selectable speed (where fs is the audio sam- pling frequency). plus, the divide-by 1, 2, or 4 counter settings means that external clocks of 768fs/ 384fs/192fs (192fs input) and 1024fs/512fs/256fs (256fs input) are supported. the SM5847af operates from a single 3 to 5 v sup- ply, and is available in 44-pin qfp packages. features n left/right-channel (2-channel processing) n 4-times/8-times oversampling (interpolation) 8-times interpolation ?ter - 3-stage linear-phase fir con?uration 1st stage (fs to 2fs): 169-tap 2nd stage (2fs to 4fs): 29-tap 3rd stage (4fs to 8fs): 17-tap - ?.00002 db passband ripple (0 to 0.4535fs) - 3 117 db stopband attenuation (0.5465fs to 7.4535fs) 4-times interpolation ?ter - 2-stage linear-phase fir con?uration 1st stage (fs to 2fs): 169-tap 2nd stage (2fs to 4fs): 29-tap - ?.00002 db passband ripple (0 to 0.4535fs) - 3 116 db stopband attenuation (0.5465fs to 3.4535fs) n digital deemphasis iir ?ter con?uration fs = 32khz, 44.1khz, 48khz 2-channel independent on/off control n 26 24-bit parallel multiplier/32-bit accumulator n over?w limiter n soft muting 2-channel independent on/off control n input data format 2s complement, msb ?st 3 selectable formats - lr alternating, 16/18/20/24-bit serial, right- justi?d data - lr alternating, 24-bit serial, left-justi?d data - lr simultaneous, 24-bit serial, left-justi?d data n output data format 2s complement, msb ?st, lr simultaneous 18/20/22/24-bit serial bcko burst (npc format) n dither round-off processing dither round-off on/off selectable n 25-bit internal data word length n internal system clock 192fs/256fs selectable maximum operating frequency 192fs mode: 37 mhz max (5 v) 20.7 mhz max (3 v) 256fs mode: 27.6 mhz max (5 v) 25 mhz max (3 v) n jitter-free function jitter-free/sync mode selectable n crystal oscillator circuit built-in n 3 to 5 v supply n 44-pin plastic qfp n cmos process ordering information device package SM5847af 44-pin qfp
SM5847af nippon precision circuits? pinout (top view) package dimensions (unit: mm) 44-pin plastic qfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 omd dor dol wcko bcko vss vssac vddac vdd dg nc rstn syncn ow2n ow1n vdd vss iw2n/dir iw1n/dil inf1n cksln nc cko vss vdd xto xti vss vdd lrci di/inf2n bcki nc dithn muter mutel fsel2 fsel1 vss vdd dempl dempr ckdv2 ckdv1 sm58 4 7af 12.80 0.30 + - 0.35 0.10 + - 0.20 m 4 c 0.7 - - 0.15 0.05 + 0.15 + - 0.60 0.20 - 0.17 0.05 + - 0.17 0.05 + 12.80 0.30 + - 10.00 0.30 + - 10.00 0.30 + - - 1.50 0.10 + 0.20 0.80 (1.40) 0 to 10 (1.40)
SM5847af nippon precision circuits? block diagram output data interface block input data interface system clock bcko dor xti xto cko dempr mutel rstn wcko dol timing controller syncn fsel1 fsel2 vdd vss ow1n lrci di/inf2n inf1n filter and attenuation arithmetic block deemphasis controller ow2n dg vddac vssac mute controller muter iw1n/dil iw2n/dir dempl dithn cksln ckdv1 ckdv2 bcki omd
SM5847af nippon precision circuits? pin description number name i/o description 1 omd ip 1 1. schmitt input, ttl level output data r ate (4fs/8fs) select pin 2 dor o 2 2. ttl level ip = pull-up input right-channel data output 3 dol o 2 left-channel data output 4 wcko o 2 w ord clock output 5 bcko o 2 bit clock output 6 vss ground 7 vssac ground 8 vddac supply voltage 9 vdd supply voltage 10 dg o 2 deglitched signal output 11 n c no inter nal connection (must be open) 12 cko o 2 master clock output 13 vss ground 14 vdd supply voltage 15 xto o oscillator output 16 xti i oscillator input/master clock input 17 vss ground 18 vdd supply voltage 19 lrci i 1 input data sample r ate (fs) clock input 20 di/inf2n i 1 data input/input format select pin 2 21 bcki i 1 bit clock input 22 n c no inter nal connection (must be open) 23 n c no inter nal connection (must be open) 24 cksln ip 2 master clock frequency (192fs/256fs) select pin 25 inf1n ip 2 input for mat select pin 1 26 iw1n/dil ip 1 input data w ord length select pin 1/left-channel data input 27 iw2n/dir ip 1 input data w ord length select pin 2/right-channel data input 28 vss ground 29 vdd supply voltage 30 ow1n ip 2 output data w ord length select pin 1 31 ow2n ip 2 output data w ord length select pin 2 32 syncn ip 2 sync mode select pin 33 rstn ip 1 reset input 34 ckdv1 ip 1 inter nal system clock frequency divider set pin 1 35 ckdv2 ip 1 inter nal system clock frequency divider set pin 2 36 dempr ip 1 right-channel deemphasis on/off pin 37 dempl ip 1 left-channel deemphasis on/off pin 38 vdd supply voltage 39 vss ground 40 fsel1 ip 1 deemphasis lter sample rate (fs) select pin 1 41 fsel2 ip 1 deemphasis lter sample rate (fs) select pin 2 42 mutel ip 1 left-channel m ute on/off pin 43 muter ip 1 right-channel mute on/off pin 44 dithn ip 1 output data dither on/off pin
SM5847af nippon precision circuits? specifications absolute maximum ratings v ss = v ssac = 0 v, v dd = v ddac recommended operating conditions v ss = v ssac = 0 v, v dd = v ddac v ss = v ssac = 0 v, v dd = v ddac parameter symbol condition rating unit supply v oltage r ange 1 1. supply lines for vdd and vddac, and ground lines for vss and vssac, should be connected on the pr inted circuit board to prev ent device break- down due to potential diff erence when the power is applied. v dd , v ddac - 0.3 to 6.5 v input voltage r ange v i v ss - 0.3 to v dd + 0.3 v stor age temper ature r ange t stg - 55 to 125 c pow er dissipation p d 70 c 900 mw 85 c 700 parameter symbol rating unit supply v oltage r ange 1 1. the minimum required oper ating v oltage and consequent operating temper ature vary with the maximum oper ating frequency and sampling mode selected, as shown in the follo wing table. v dd , v ddac 3.00 to 5.25 v oper ating temper ature r ange t a - 40 to 85 c sampling frequency fs (khz) internal system clock minimum supply v oltage v dd , v ddac (v) operating temperature t a ( c) mode 1 1. mode with internal frequency divider ratio set to 1 (ckdv1 = ckdv2 = low). maximum operating frequency (mhz) 192 192fs 37 4.75 (5.0 - 5%) - 40 to 70 256fs not guar anteed not guar anteed not guar anteed 108 2 2. 96 khz + 12.5% variable pitch 192fs 20.7 3.00 (3.3 - 10%) - 40 to 85 256fs 27.6 4.50 (5.0 - 10%) 96 192fs 18.5 3.00 (3.3 - 10%) 256fs 25 3.00 (3.3 - 10%) 55.2 3 3. 48 khz + 15% variable pitch 192fs 10.6 3.00 (3.3 - 10%) 256fs 14.2 3.00 (3.3 - 10%)
SM5847af nippon precision circuits? dc electrical characteristics v dd = v ddac = 3.00 to 5.25 v, v ss = v ssac = 0 v, t a = - 40 to 85 c v dd = v ddac = 4.75 to 5.25 v, v ss = v ssac = 0 v, t a = - 40 to 85 c, xti = external input, no output load v dd = v ddac = 3.00 to 3.60 v, v ss = v ssac = 0 v, t a = - 40 to 85 c, xti = external input, no output load parameter symbol condition rating unit min typ max high-level input v oltage 1 1. pin xti v ih1 0.7v dd v high-level input v oltage 2,4 2. pins lrci, di/inf2n, bcki v ih2 2.0 v high-level input v oltage 3 3. pins iw1n/dil, iw2n/dir v ih3 v dd = v ddac = 4.75 to 5.25 v 2.4 v v dd = v ddac = 3.00 to 4.75 v 2.0 l ow -level input v oltage 1 v il1 v dd = v ddac = 4.75 to 5.25 v 0.3v dd v v dd = v ddac = 3.00 to 4.75 v 0.2v dd l ow -level input v oltage 2,4 v il2 v dd = v ddac = 4.75 to 5.25 v 0.8 v v dd = v ddac = 3.00 to 4.75 v 0.2v dd l ow -level input v oltage 3 v il3 v dd = v ddac = 4.75 to 5.25 v 0.8 v v dd = v ddac = 3.00 to 4.75 v 0.2v dd input leakage current 1,2 i il1 v in = 0 to 5.25 v - 10 10 a input current 3,4 4. pins omd, cksln, inf1n, o w1n, ow2n, syncn, rstn, ckd v1, ckdv2, dempr, dempl, fsel1, fsel2, mutel, muter, dithn i il2 v in = 0 v - 10 - 50 - 120 a high-level output v oltage 5 5. pins dor, dol, w c ko, bcko, dg, cko v oh i oh = - 4 ma 2.4 v low -level output v oltage 5 v ol i ol = 4 ma 0.4 v parameter symbol condition rating unit min typ max current consumption i dd1 192fs, xti = 27 ns (37 mhz), fs = 192 khz,t a = - 40 to 70 c 166 ma i dd2 256fs, xti = 40 ns (25 mhz), fs = 96 khz 115 ma i dd3 384fs, xti = 27 ns (37 mhz), fs = 96 khz, estimated value 105 ma i dd4 192fs, xti = 54 ns (18.5 mhz), fs = 96 khz, estimated value 95ma i dd5 384fs, xti = 54 ns (18.5 mhz), fs = 48 khz, estimated value 65ma parameter symbol condition rating unit min typ max current consumption i dd6 256fs, xti = 81 ns (12.3 mhz), fs = 48 khz, estimated value 27ma i dd7 384fs, xti = 54 ns (18.5 mhz), fs = 48 khz, estimated value 28ma
SM5847af nippon precision circuits? ac electrical characteristics crystal oscillator (xti, xto) v dd = v ddac = 3.00 to 5.25 v, v ss = v ssac = 0 v, t a = - 40 to 85 c external clock input (xti) v dd = v ddac = 3.00 to 5.25 v, v ss = v ssac = 0 v, t a = - 40 to 85 c internal system clock the crystal oscillator frequency or external clock input master clock frequency ratings are described in the pre- ceding tables, but it is the internal system clock frequency rating, set by the internal frequency divider (ckdv1, ckdv2), that must be satis?d. the master clock frequency is a multiple of the sampling frequency fs. ckdv1 = ckdv2 = low (internal system clock frequency = xti input frequency), v ss = v ssac = 0 v, t a = - 40 to 85 c parameter symbol condition rating unit min typ max oscillator frequency 1 1. external circuit components should be matched for the crystal oscillator element used. f osc 50 mhz parameter symbol condition rating unit min typ max master clock frequency f xti 60 mhz master clock duty 1/2v dd thresholds 40 60 % parameter symbol condition rating unit min typ max 256fs (cksln = low, ckdv1 = low, ckdv2 = low) system clock frequency f sys1 v dd = v ddac = 4.50 to 5.25 v 0.256 27.6 mhz v dd = v ddac = 3.00 to 5.25 v 0.256 25 192fs (cksln = high, ckdv1 = low, ckdv2 = low) system clock frequency f sys2 v dd = v ddac = 4.75 to 5.25 v, t a = - 40 to 70 c 0.384 37 mhz v dd = v ddac = 3.00 to 5.25 v 0.384 20.7
SM5847af nippon precision circuits? serial input timing ( bcki, lrci, di/inf2n, iw1n/dil, iw2n/dir) v ss = v ssac = 0 v, t a = - 40 to 85 c 1. cksln = high (192fs), v dd = v ddac = 4.75 to 5.25 v, t a = - 40 to 70 c 2. cksln = low (256fs), v dd = v ddac = 4.50 to 5.25 v cksln = high (192fs), v dd = v ddac = 3.00 to 4.75 v 3. cksln = low (256fs), v dd = v ddac = 3.00 to 4.50 v parameter symbol condition rating unit min typ max bcki pulse cycle t ibcy note 1 55 ns note 2 80 note 3 100 bcki high-level pulse width t bcwh note 1 25 ns note 2 35 note 3 45 bcki low -level pulse width t bcwl note 1 25 ns note 2 35 note 3 45 di, dil, dir setup time t ds note 1 10 ns note 2 20 note 3 30 di, dil, dir hold time t dh note 1 10 ns note 2 20 note 3 30 last bcki rising edge to lrci edge t bl note 1 10 ns note 2 20 note 3 30 lrci edge to rst bcki rising edge t lb note 1 10 ns note 2 20 note 3 30 lrci 1.5v bcki t ibcy t bcwh t bcwl t ds t dh t bl t lb di dil dir 1.5v 1.5v
SM5847af nippon precision circuits? reset timing (rstn) v dd = v ddac = 3.00 to 5.25 v, v ss = v ssac = 0 v, t a = - 40 to 85 c output timing (cko, bcko, wcko, dol, dor, dg) v dd = v ddac = 4.75 to 5.25 v, v ss = v ssac = 0 v, t a = - 40 to 70 c, c l = 50 pf parameter symbol condition rating unit min 1 1. t mck is equal to 1/f xti or 1/f osc . for example, t rst = 54 ns when f xti = 37 mhz. typ max rstn low-level reset pulse width t rst 2t mck ns parameter symbol condition rating unit min typ max xti falling edge to cko falling edge delay t xto 4?ns v dd = v ddac = 3.00 to 5.25 v, t a = - 40 to 85 c 411ns b c ko falling edge to w c ko , dol, dor, dg delay t bdo - 4 2ns b c ko rising edge to w c ko falling edge t woh output mode: 8fs omd = high (fs = 192 khz) exter nal clock input: xti = 27 ns (37 mhz), cksln = high (192fs) divider r atio: 1 ckdv1 = ckdv2 = low output data length: 24 bits ow1n = ow2n = low 8ns w c ko falling edge to bcko rising edge t wos 8ns bcko period t obcy 27 ns bcko high-level pulse width t obch 7ns b c ko low -level pulse width t obcl 7ns dol, dor setup time t ods 7ns dol, dor hold time t odh 7ns b c ko rising edge to w c ko falling edge t woh output mode: 4fs omd = low (fs = 192 khz) exter nal clock input: xti = 27 ns (37 mhz), cksln = high (192fs) divider r atio: 1 ckdv1 = ckdv2 = low output data length: 24 bits ow1n = ow2n = low 17 ns w c ko falling edge to bcko rising edge t wos 17 ns bcko period t obcy 54 ns bcko high-level pulse width t obch 18 ns b c ko low -level pulse width t obcl 18 ns dol, dor setup time t ods 18 ns dol, dor hold time t odh 18 ns 1.5v rstn t rst
SM5847af nippon precision circuits?0 v dd = v ddac = 4.50 to 5.25 v, v ss = v ssac = 0 v, t a = - 40 to 85 c, c l = 50 pf parameter symbol condition rating unit min typ max bcko high-level pulse width t obch exter nal clock input: xti = 36 ns (27.6 mhz), cksln = low (256fs), fs = 108 khz divider r atio: 1 ckdv1 = ckdv2 = low output mode: 8fs, omd = high 10 ns b c ko low -level pulse width t obcl 10 ns dol, dor setup time t ods 11 ns dol, dor hold time t odh 11 ns bcko high-level pulse width t obch exter nal clock input: xti = 36 ns (27.6 mhz), cksln = low (256fs), fs = 108 khz divider r atio: 1 ckdv1 = ckdv2 = low output mode: 4fs, omd = low 26 ns b c ko low -level pulse width t obcl 26 ns dol, dor setup time t ods 27 ns dol, dor hold time t odh 27 ns bcko 1.5v t xto xti cko 1.5v 1.5v t bdo 1.5v wcko dol dor dg t woh t wos t obcl t obch t obcy t ods 1.5v 1.5v 1.5v t odh wcko bcko dol dor
SM5847af nippon precision circuits?1 filter characteristics 8-times interpolation ?ter 8fs ?ter response with deemphasis off 8fs ?ter band transition response with deemphasis off 8fs ?ter passband response with deemphasis off parameter rating passband 0 to 0.4535fs stopband 0.5465fs to 7.4535fs passband r ipple ?.00002 db stopband atten uation 3 117 db group delay constant 0.0 1.0 2.0 4.0 5.0 6.0 7.0 8.0 140 120 100 80 60 40 20 0 attenuation 3.0 (db) frequency ( fs) 0.000 0.125 0.250 0.375 0.500 0.00008 0.00004 0.00000 -0.00004 -0.00008 attenuation (db) frequency ( fs) 0.440 0.465 0.490 0.515 0.540 0.565 0.590 0.615 0.640 frequency ( fs) 140 120 100 80 60 40 20 0 attenuation (db)
SM5847af nippon precision circuits?2 4-times interpolation ?ter 4fs ?ter response with deemphasis off 4fs ?ter band transition response with deemphasis off 4fs ?ter passband response with deemphasis off parameter rating passband 0 to 0.4535fs stopband 0.5465fs to 3.4535fs passband r ipple ?.00002 db stopband atten uation 3 116 db group delay constant 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 frequency ( fs) 140 120 100 80 60 40 20 0 attenuation (db) 0.000 0.125 0.250 0.375 0.500 frequency ( fs) 0.00008 0.00004 0.00000 -0.00004 -0.00008 attenuation (db) 0.440 0.465 0.490 0.515 0.540 0.565 0.590 0.615 0.640 140 120 100 80 60 40 20 0 frequency ( fs) attenuation (db)
SM5847af nippon precision circuits?3 deemphasis ?ter passband response with deemphasis on parameter sampling frequency (fs) 32 khz 44.1 khz 48 khz passband bandwidth (khz) 0 to 14.5 0 to 20.0 0 to 21.7 deviation from ideal character istic attenuation ?.01 db phase, q 0 to 1.5 10 100 1k 10k 20 50 200 500 2k 5k 20k 8 6 4 2 0 -60 -40 -20 0 phase (degrees) 32khz 44.1khz 48khz phase 32khz 44.1khz 48khz attenuation (db) frequency ( hz ) [hz] attenuation 10
SM5847af nippon precision circuits?4 functional description oversampling (interpolation) the interpolation arithmetic block is comprised of 3 cascaded, 2-times fir interpolation ?ters, as shown in ?ure 1. the input signal is sampled at rate fs, and then either 4-times or 8-times oversampling data is output. sampling noise in the 0.5465fs to 3.4535fs (4fs output) or 0.5465fs to 7.4535fs (8fs output) region is removed. figure 1. arithmetic operating block input fs 2-times interpolator 1st fir 169-tap 2fs 2-times interpolator 2nd fir 29-tap 4fs deemphasis iir filter deemphasis on 4fs soft mute 4fs 8fs output deemphasis off 2 -times interpolator 3rd fir 17-tap 4fs
SM5847af nippon precision circuits?5 digital deemphasis (dempl, dempr, fsel1, fsel2) most deemphasis ?ters are constructed using analog circuit techniques. here, an iir ?ter is employed to faithfully reproduce the gain and phase characteris- tics of standard analog deemphasis ?ters, corre- sponding to analog 50?/15? frequency characteristics. three sets of ?ter coef?ients for the three fs = 32/44.1/48 khz sampling frequencies are supported. deemphasis for other values of fs are not supported. deemphasis on/off (dempl, dempr) deemphasis for the left and right-channel can be controlled independently. filter coef?ient select (fsel1, fsel2) soft muting (mutel, muter) the muting function controls the muting of left and right-channel independently. input data continues to be accepted even when mute is operating. mute on/off when mutel (muter) goes high, the attenua- tion changes smoothly from 0 to - db. similarly, when mutel (muter) goes low, muting is released and the attenuation changes smoothly from - to 0 db. this operation is termed soft muting. soft muting takes an interval of approximately 512/fs, or about 11.6 ms when fs = 44.1 khz. mute operation at reset when rstn goes low, the dol and dor outputs are immediately muted to - db. when rstn goes high, reset is released and the outputs are immedi- ately set to 0 db attenuation. note that even when either mutel or muter or both are high, the reset operation takes precedence. table 1. deemphasis control dempl dempr deemphasis low left-channel off high left-channel on low right-channel off high right-channel on table 2. deemphasis ?ter coef?ient select fsel1 fsel2 sampling frequency (fs) low low 44.1 khz low high 48 khz high low prohibited mode high high 32 khz table 3. mute control mutel muter soft m uting low left-channel off high left-channel on low right-channel off high right-channel on
SM5847af nippon precision circuits?6 analog output click noise under the following conditions, a click noise may be output from the dac (digital-to-analog converter) connected to the SM5847af. n when a system reset on rstn occurs n when the internal system clock mode, set by cksln, ckdv1, and ckdv2, is switched n when the deemphasis mode, set by dempl, dempr, fsel1, and fsel2, is switched n when the audio data input mode, set by inf1n, di/inf2n, iw1n/dil, and iw2n/dir, is switched n when the syncn jitter-free mode switch timing exceeds the internal timing delay limit an external muting circuit connected to the analog output may be required to eliminate this noise. figure 2. soft muting/reset operation 512/fs 512/fs normal operation reset reset soft mute soft mute di/inf2n, iw1n/dil, iw2n/dir rstn mutel/muter gain external dac analog output (full scale signal) l lh h +fs zero -fs h lh l click noise 0db fs: full scale -
SM5847af nippon precision circuits?7 internal system clock (xti, x to, cko, cksln, ckdv1, ckdv2) the SM5847af supports two system clock frequen- cies selected by cksln, 192fs and 256fs, where fs is the sampling frequency. the master clock can be provided either by a crystal oscillator connected between xti and xto, or by an external master clock input on xti. note that the feedback resistor required by the oscillator option is not built-in. external components should be selected to match the crystal oscillator element. note also that xto must be left open (?ating) for the external master clock input option. note that even though it is necessary that the master clock and lrci clock (sampling frequency fs) be in sync, it is not necessary that they be exactly in-phase (see jitter-free mode description). the SM5847af features independent divide-by 1, 2, or 4counter, selected by ckdv1 and ckdv2. this provides the 192fs or 256fs system clock with the necessary divider ratios to support master clocks with frequencies of 768fs, 384fs, 192fs, 1024fs, 512fs or 256fs. normal sampling frequencies 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz and 192 khz are supported. however, some combinations of sam- pling frequency and master clock frequency are not supported, as follows. n 768fs and 1024fs at 88.2 and 96 khz n 768fs, 384fs, 1024fs, 512fs, and 256fs at 176.4 khz n 768fs, 384fs, 1024fs, 512fs and 256fs at 192 khz note also that the internal crystal oscillator circuit cannot operate at frequencies 3 50 mhz. the master clock input on xti is output on cko. master clock stop operation the master clock is input after power is applied. but if, after the xti and lrci clocks are input and power-on reset occurs with all-zero input audio data, the master clock input on xti is held either high or low level, operation effectively stops. note also that a reset signal is not accepted when the master clock and lrci clock stop. table 4. internal system clock select cksln system clock low 256fs high 192fs table 5. system clock frequency divider ratio select ckdv1 ckdv2 divider ratio master clock low low 1 192fs, 256fs low high prohibited mode high low 4 768fs, 1024fs high high 2 384fs ,512fs figure 3. crystal oscillator connection figure 4. external clock connection c 1 c 2 xtal xti xto 16 15 12 r1 cko divider master clock buffer output SM5847af xti xto 16 15 12 cko divider master clock buffer output SM5847af external clock xto : open
SM5847af nippon precision circuits?8 system reset (rstn) during normal device operation, reset signals are not required. however, the SM5847af must be reset under the following conditions. n at power-on n when the lrci clock and internal operation tim- ing need to be resynchronized in jitter-free mode. n after the lrci or xti clocks, or both, stop and are subsequently started. the system is reset by applying a low-level pulse on rstn. when rstn is low, the dol and dor outputs are tied low, muting the output signal to an attenuation level of - . after system reset, when rstn goes high, the arithmetic and output timing counters are reset on the ?st lrci start edge, assuming that the xti and lrci input clocks have already stabilized. the lrci start edge is determined by the state of inf1n and inf2n. when inf1n is low or when both inf1n and inf2n are high, the start edge is the rising edge. when inf1n is high and inf2n is low, the start edge is the falling edge. table 6. master clock frequency example sampling frequency fs (khz) xti system clock frequency (mhz) cksln = high (192fs) cksln = low (256fs) ckdv1 ckdv2 ckdv1 ckdv2 ckdv1 ckdv2 ckdv1 ckdv2 ckdv1 ckdv2 ckdv1 ckdv2 low low high high high low low low high high high low 192fs 384fs 768fs 256fs 512fs 1024fs 32 6.144 12.288 24.576 8.192 16.384 32.768 44.1 8.4627 16.9344 33.8688 11.2896 22.5792 45.1584 48 9.216 18.432 36.864 12.288 24.576 49.152 88.2 16.9344 33.8688 not guar anteed 1 1. refer to the ac char acteristics system clock ratings. 22.5792 45.1584 not guar anteed 96 18.432 36.864 not guar anteed 24.576 49.152 not guar anteed 176.4 33.8688 not guar anteed not guar anteed not guar anteed not guar anteed not guar anteed 192 36.864 not guar anteed not guar anteed 1 not guar anteed not guar anteed not guar anteed figure 5. system reset timing and output muting (inf1n = low or inf1n = inf2n = high) lrci rstn wcko omd=h 8fs rstn=l omd=l 4fs dol/dor zero internal reset
SM5847af nippon precision circuits?9 audio data input (inf1n, di/inf2n, iw1n/dil, iw2n/dir, bcki, lrci) the input data format and input pin functions are selected by the state of inf1n and inf2n. when inf1n is low, the inputs are left and right-channel data inputs, and when inf1n is high, the di/inf2n input is an input format select pin, and dil and dir are the audio data inputs. input data format select input data word length the input data word length is selected by the state of iw1n and iw2n when inf1n is low. 20-bit is selected when inf1n is high. jitter-free function (syncn) the arithmetic circuit and output control timing is derived from the system clock, and is therefore inde- pendent of the input lrci and bcki clocks. accordingly, any jitter in the data input clock (lrci and bcki) does not cause jitter in the output. generally, the internal timing is synchronized to the lrci input timing after a system reset release, when rstn goes from low to high, on the ?st lrci clock start edge. if the input timing and lrci start edge timing subsequently drift, the input timing is automatically resynchronized when the timing error exceeds a certain value. there are 2 timing error val- ues at which resynchronization occurs, selected by the state of syncn. jitter-free mode (syncn = high) when syncn is high, the timing error value is ?/8 (lrci clock period). when the difference between the input timing and lrci start edge posi- tion do not exceed this value, internal timing is not resynchronized and all functions continue to operate normally. sync mode (syncn = low) when syncn is low, the timing error value is ? (xti master clock period), which is a much smaller timing error tolerance than in jitter-free mode. in this mode, the internal timing is guaranteed to follow the lrci clock timing within this toler- ance, making this mode useful for systems con- structed from a multiple number of SM5847af devices. table 7. input settings and functions inf1n di/inf2n input format pin function selection di/inf2n iw1n/dil iw2n/dir low - lr alternating 1 , right-justi?d data 1. alternating left-channel and right-channel data input on a single input di. di iw1n iw2n low - high low lr alter nating, left-justi?d data inf2n dil dir high high lr sim ultaneous 2 , left-justi?d data 2. simultaneous left-channel and right-channel data input on two inputs, dil and dir, respectively. table 8. input data word length select inf1n iw1n/dil iw2n/dir input word length low low low 24 bits high low 20 bits low high 18 bits high high 16 bits high 24 bits
SM5847af nippon precision circuits?0 audio data output (dol, dor, bcko, wcko, dg, ow1n, ow2n, omd, dithn) output data format the output data is in serial, simultaneous left and right-channel, 2s complement, msb ?st, bcko burst (npc format) format. left-channel data is out- put on dol, and right-channel data is output on dor. output data word length the output data word length is selected by the state of ow1n and ow2n. output timing the output timing is dependent on the cksln level and output data word length. when cksln is low, the output timing does not change with the output data word length. however, when cksln is high, the dol and dor output timing for 24-bit output data length (ow1n = ow2n = low) start 1 clock cycle earlier than for 18, 20, or 22-bit output data length. output mode the output mode, either 4fs oversampling or 8fs oversampling, is selected by the level on omd, where fs is the input sampling rate. output dither processing the output data word length is set by ow1n and ow2n, whereas the SM5847af performs all inter- nal calculations in 25-bit words. as a consequence, dither processing is provided to round-off errors. the SM5847af uses triangular dither processing (trian- gular probability density function or tpdf) and can be turned on or off. simple round-off processing occurs when dither is off (dithn = high). table 9. output data word length select ow1n ow2n output word length low low 24 bits high low 22 bits low high 20 bits high high 18 bits table 10. output timing parameter symbol cksln omd = high omd = low bit clock rate t b high 1/192fs 1/96fs low 1/256fs 1/128fs data w ord length t dw high 24t sys 48t sys low 32t sys 64t sys table 11. output mode select omd output mode low 4fs high 8fs table 12. dither select dithn dither low on high off
SM5847af nippon precision circuits?1 group delay the data input to data output group delay is the delay which occurs due to the digital ?ter calculations. it is the time between the serial input data is com- pletely read in (at rate fs) until the serial data is out- put (at rate 8fs or 4fs, depending on the mode selected). t input represents the lrci clock rising edge after the serial input data has been read in at rate fs. t output represents the wcko clock falling edge at the start of serial data output at rate 8fs or 4fs. table 13. group delay mode gr oup delay unit cksln syncn t output - t input low (256fs) low after reset, or sync mode 48.625/fs sec high jitter-free mode 48.25/fs - 49.0/fs high (192fs) low after reset, or sync mode 48.75/fs high jitter-free mode 48.375/fs - 49.125/fs figure 6. group delay timing (syncn = low) 1/fs lrci wcko 8fs omd=h t output cksln=l (256fs) wcko 4fs omd=l wcko 8fs omd=h t output wcko 4fs omd=l t output t output serial data output (dol,dor) cksln=h (192fs) t input 1/fs lrci 48/fs serial data input (di/inf2n, iw1n/dil, iw2n/dir) serial data output (dol,dor) serial data output (dol,dor) serial data output (dol,dor)
SM5847af nippon precision circuits?2 timing diagrams input timing examples *1: optional bcki clock cycles figure 7. lr alternating, right-justi?d data, 2s complement, msb ?st, inf1n = l lrci 1 / fs bcki di/ inf2n 16bit 1 16 116 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 msb lsb 1 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 msb lsb 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 msb lsb 1 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 msb lsb 17 18 1 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 msb lsb 17 18 17 18 19 20 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 msb lsb 17 18 19 20 17 18 19 20 21 22 23 24 1 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 msb lsb 17 18 19 20 21 22 23 24 lch rch bcki di/ inf2n 18bit bcki di/ inf2n 20bit bcki di/ inf2n 24bit *1 iw1n/dil = h, iw2n/dir = h iw1n/dil = l, iw2n/dir = h iw1n/dil = h, iw2n/dir = l iw1n/dil = l, iw2n/dir = l don't care don't care don't care don't care don't care don't care don't care don't care
SM5847af nippon precision circuits?3 *1: there m ust be a minimum of 24 bcki clock cycles. data input after the lsb is ignored. figure 8. lr alternating, left-justi?d data, 2s complement, msb ?st, inf1n = h, di/inf2n = l, 24-bit *1: there m ust be a minimum of 24 bcki clock cycles. data input after the lsb is ignored. figure 9. lr simultaneous, left-justi?d data, 2s complement, msb ?st, inf1n = h, di/inf2n = h, 24-bit lrci 1 / fs lch rch *1 1 24 1 24 bcki iw1n/dil 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 msb lsb 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 msb lsb 17 18 19 20 21 22 23 24 iw2n/dir don't care don't care don't care don't care bcki 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 lrci iw1n/dil iw2n/dir msb msb lsb lsb 1 / fs * 1 1 24 don't care don't care
SM5847af nippon precision circuits?4 output timing examples figure 10. 2s complement, msb ?st, cksln = h, omd = h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 msb lsb wcko 1 / 8fs bcko dol dor 1 18 bcko dol dor 1 20 bcko dol dor 1 22 bcko 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 dol dor msb msb 1 24 dg 1 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 msb lsb lsb lsb 10 12 22 t b t dw 18bit ow1n = h ow2n = h 20bit ow1n = l ow2n = h 22bit ow1n = h ow2n = l 24bit ow1n = l ow2n = l 192fs internal system clock
SM5847af nippon precision circuits?5 figure 11. 2s complement, msb ?st, cksln = h, omd = l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 msb lsb wcko 1 / 4fs bcko dol dor 1 18 bcko dol dor 1 20 bcko dol dor 1 22 bcko 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 dol dor msb msb 1 24 dg 2 48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 msb lsb lsb lsb 20 24 44 t b t dw 18bit ow1n = h ow2n = h 20bit ow1n = l ow2n = h 22bit ow1n = h ow2n = l 24bit ow1n = l ow2n = l 192fs internal system clock
SM5847af nippon precision circuits?6 figure 12. 2s complement, msb ?st, cksln = l, omd = h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 msb lsb wcko 1 / 8fs bcko dol dor 1 18 bcko dol dor 1 20 bcko dol dor 1 22 bcko dol dor dg 1 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 msb lsb 14 16 32 t b t dw 18bit ow1n = h ow2n = h 20bit ow1n = l ow2n = h 22bit ow1n = h ow2n = l 24bit ow1n = l ow2n = l 256fs internal system clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 msb msb 1 24 lsb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 msb lsb 30
SM5847af nippon precision circuits?7 figure 13. 2s complement, msb ?st, cksln = l, omd = l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 msb lsb wcko 1 / 4fs bcko dol dor 1 18 bcko dol dor 1 20 bcko dol dor 1 22 bcko dol dor dg 2 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 msb lsb 28 32 64 t b t dw 18bit ow1n = h ow2n = h 20bit ow1n = l ow2n = h 22bit ow1n = h ow2n = l 24bit ow1n = l ow2n = l 256fs internal system clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 msb msb 1 24 lsb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 msb lsb 60
SM5847af nippon precision circuits?8 typical application (1) this circuit shows a basic connection to a 24-bit input dac (sm5865bm). 36.864 mhz external clock, 48/96/192 khz sam- pling rate fs, 24-bit data, 8fs oversampling operation (note that certain circuit details required for good dac analog output characteristics have been omit- ted.) figure 14. SM5847af and sm5865bm connection table 14. operating mode select sampling frequency fs (khz) internal system clock frequency divider ratio select output mode select external clock xti (mhz) cksln = high (192fs) mode ckdv1 ckdv2 divider o m d output mode 48 768fs high low 4 high 8fs 36.864 96 384fs high high 2 high 8fs 192 192fs low low 1 high 8fs omd 36.864mhz ckdv1 ckdv2 fs 24-bit data bit clock cksln bcko wcko dol dor inf1n iw1n/dil ow1n ow2n iw2n/dir vss vdd vdd vddac vssac vss avssa dvdd ckdvn cvss bcki wcki tstn SM5847af sm5865bm rstn i/v converter +5v ckdv1 ckdv2 vdd vss bcki di/inf2n lrci vdd vss xti xto vdd vss 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 3 4 5 6 7 8 9 10 11 12 13 22 21 20 19 18 17 16 15 14 omd 1 2 24 23 di dvss iwsl rstn to cki rap iouta ioutan ran avdda avddb rbp ioutb ioutbn rbn avssb avssa dvdd ckdvn cvss bcki wcki tstn 3 4 5 6 7 8 9 10 11 12 13 22 21 20 19 18 17 16 15 14 1 2 24 23 di dvss iwsl rstn to cki rap iouta ioutan ran avdda avddb rbp ioutb ioutbn rbn avssb sm5865bm +5v i/v converter i/v converter i/v converter
SM5847af nippon precision circuits?9 typical application (2) this circuit shows a basic connection to a 24-bit input dac (burr-brown pcm1704u). 36.864 mhz external clock, 48/96/192 khz sam- pling rate fs, 24-bit data, 8fs or 4fs oversampling operation (note that certain circuit details required for good dac analog output characteristics have been omitted.) figure 15. SM5847af and burr-brown pcm1704u connection table 15. operating mode select sampling frequency fs (khz) internal system clock frequency divider ratio select output mode select external clock xti (mhz) cksln = high (192fs) mode ckdv1 ckdv2 divider o m d output mode 48 768fs high low 4 high 8fs 36.864 96 384fs high high 2 high 8fs 192 192fs low low 1 low 4fs omd 36.864mhz ckdv1 ckdv2 fs 24-bit data bit clock cksln bcko wcko dol dor inf1n iw1n/dil ow1n ow2n iw2n/dir vss vdd vdd vddac vssac vss agnd agnd dd wclk 20bit invert data bclk dd dgnd -v cc +vcc agnd agnd +vdd wclk 20bit invert data bclk -v dd dgnd -v cc +v cc SM5847af pcm1704u pcm1704u i out i out rstn i/v converter +5v -5v +5v ckdv1 ckdv2 vdd vss bcki di/inf2n lrci vdd vss xti xto vdd vss 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 20 19 18 17 16 15 14 13 12 omd +v -v i/v converter
SM5847af nippon precision circuits?0 nippon precision circuits inc. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. nippon precision circuits inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infr ingement. applications for any devices shown in this data sheet are for illustr ation only and nippon precision circuits inc. makes no claim or warranty that such applications will be suitable for the use speci?d without further testing o r modi?ation. the products described in this data sheet are not intended to use for the apparatus which in uence human lives due to the failure or malfunction of the products. customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, including compliance with export controls on the distribution or dissemination of the products. customers shall not e xport, directly or indirectly, any products without ?st obtaining required licenses and approv als from appropriate gover nment agencies. nippon precision circuits inc. 4-3, fukuzumi 2-chome koto-ku, tokyo 135-8430, j apan telephone: 03-3642-6661 facsimile: 03-3642-6698 nc9803de 2000.2 nippon precision circuits inc.

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